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SAA7893hl super audio media player rev. 02 26 february 2003 product data 1. general description thanks to the superior sound quality and multichannel capability of super audio cd (sacd) technology, multimedia devices such as dvd players and home cinema systems are incorporating sacd functionality. philips' super audio media player (sa-mp) provides a ?exible, state-of-the-art solution for sacd playback on dvd architectures. built around the SAA7893hl sacd processor, sa-mp system solution delivers complete sacd functionality, avoiding the need for continual redesign and re-integration of sacd into various applications. the system is completed with a single 64 mbit sdram and has extensive software processing options, resulting in low total system cost (see figure 1 ). with integrated support for multiple loaders, the SAA7893 supports a variety of dvd platforms. high level and standard software interfaces C optimized for easy design-in C further enhance adaptability, enabling designers to build sacd players on many different hardware and software platforms. this ensures that the sa-mp can be left unchanged even if the sacd playback hardware is altered, again minimizing development effort. fig 1. general block diagram. psp decoder sacd demux dst decoder be switch hw 64 mbit sdram dvd host dvd host dac out mgu724 d/a dsd postprocessor pcm converter dsd converter dac switch hw annex j+ playback api sacd text and data api speaker setup api SAA7893hl sa-mp sw dvd sw stack dvd host ic
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 2 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 1.1 hardware the sa-mp hardware consists of the SAA7893hl device. a typical hw block diagram of a dvd system incorporating the SAA7893hl is shown in figure 2 . the SAA7893hl takes sector data from the front-end. the front-end is controlled by the dvd host via the sa-mp software stack. the SAA7893hl uses one 64 mbit sdram for audio data buffering and storage of sacd tocs. the front-end timing can be fully asynchronous from all clocks. the 6-channel dac outputs of the dvd host are routed via the SAA7893hl which provides a dac switch function between sacd mode and dvd mode. the audio outputs of the SAA7893hl operate on the system audio clock. the dvd back-end communicates with the SAA7893hl via a host bus. the system clock and the system audio clock are allowed to be asynchronous. 1.2 software the sa-mp software is delivered in the form of a library in the development environment of the dvd host. the sa-mp software has been developed in ansi-c using conventional software technology to allow easy integration into any development environment. a typical software block diagram of a dvd system incorporating sa-mp is shown in figure 3 . at the device driver and hw-level, sa-mp interfaces with the SAA7893hl and a front-end driver. at the infrastructure level, sa-mp interfaces with an operating system abstraction layer (osa). at the application level, sa-mp provides a high-level playback and post-processing interface which is easy to integrate into typical applications. fig 2. hardware block diagram. dvd back-end front- end SAA7893hl nvram rom pll 27 mhz sdram sdram video control audio mgu726 audio audio clock data host bus efm
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 3 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 2. features 2.1 components n SAA7893hl second generation sacd processor ic n sa-mp annex j+ level software stack. 2.2 hw interfaces n front-end, supports 3 types: u ude u fec u i 2 s-bus n flexible psp detection from efm signal with agc, without efm clock (digital pll) n (dvd-)host bus, supports 3 types: u separate address/data bus (sad16) with 16-bit data bus (3 different modes) u multiplexed address/data bus (mad16) with 16-bit data bus (2 different modes) u separate address/data bus (sad08) with 8-bit data bus (1 mode) n 16-bit 100 mhz sdram interface supports one 64 mbit device n 6-channel i 2 s-pcm audio input 44.1, 48, 88.2, 96, 176.4 or 192 khz at 16-bit or 24-bit n 6-channel dsd or i 2 s-pcm (2f s or 4f s ) output with programmable pinning con?guration n 2-channel dsd or i 2 s-pcm (2f s or 4f s ) output with programmable pinning con?guration n audio clock reference 256f s , 384f s , 512f s or 768f s n system clock 27 to 35 mhz. 2.3 sw interfaces n annex j+ level playback interface fig 3. software block diagram. application layer - "sacd player behaviour" annex j+ media players device drivers hw postprocessing loader etc. device drivers hw ui subsystem "look-and-feel" ui device drivers i/o peripherals mgu725 infrastructure (osa) sa-mp SAA7893hl
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 4 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. n high-level audio post-processing control n sacd data interface n system con?guration 2.4 system n full sacd menu toc and area toc storage in vbr n front-end clock asynchronous to other clocks 2.5 system con?guration n d/a converters: u dsd and pcm selectable pin sharing con?guration u dsd clock polarity n audio and system clock asynchronous n front-end type 2.6 sacd playback n sacd playback: u multi-channel u 2-channel n psp processing n decrypting and demultiplexing n vbr management n dst decoding n fade processing n annex j+ level software interface: u stop u pause u play u fast forward u fast reverse u next/previous track u program and play playlist u repeat (track, all or ab) u shuf?e u introscan u time search 2.7 audio postprocessing n dsd bass management with support of: u dolby? con?guration 0 (lll1) u dolby? con?guration 1 (sss1) u dolby? con?guration 2 (lss0) n programmable bass ?lter frequency and slope:
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 5 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. u 60, 80, 100, 120 hz u 12, 18, 24 db/oct (other frequencies or slopes are possible on customer request) n dsd down mixing: u 2/2 u 3/0 u 2/0 u separate 2/0 n dsd attenuation function 0 to - 90 db, programmable per channel n dsd delay function total 65 ms (approximately 20 meters), programmable per channel n 6-channel pcm input: u 44.1, 88.2, 176.4, 48, 96 or 192 khz at 16-bit or 24-bit u pcm to dsd upsampling with 3 programmable sigma-delta and anti-aliasing ?lter modes u attenuation and delay as with dsd n dsd to pcm conversion 88.2, 176.4 khz at 24-bit. 2.8 sacd data and text n album info n disc info n album or disc text n area text n track data n track text. 2.9 general n e-jtag for board test and debug n 3.3 v pad supply voltage n 1.8 v core supply voltage n 1.8 v analog supply voltage n lqfp128 package n 0.18 m m cmos process. 3. applications n consumer dvd players n home cinema n car audio systems.
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 6 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 4. ordering information 5. block diagram figure 4 shows the block diagram of the SAA7893hl with all de?ned functions. table 1: ordering information type number package name description version SAA7893hl lqfp128 plastic low pro?le quad ?at package; 128 leads; body 14 20 1.4 mm 2 sot425-1 fig 4. block diagram. host interface sdram interface SAA7893hl to 64 mbit sdram to host host_sel sys_clk 27-35 mhz external pcm mbl615 to dsd/pcm dac aud_clk 256/384/512/768*fs memory manager pi-bus control key hf data-bus register host interface demux decryption/ sector processor psp-key decoder adc agc sacd audio interface pi-bus control 2, 5 or 6-channel lossless decoder speaker setup volume control delay 8-channel dsd2pcm conversion switch matrix front- end interface
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 7 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 6. pinning information 6.1 pinning fig 5. pin con?guration. mce016 SAA7893hl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 h_a[1] h_dq[15] h_dq[14] gnd_io1 h_dq[13] h_dq[12] h_dq[11] h_dq[10] h_dq[9] vcc_io1 h_dq[8] h_dq[7] h_dq[6] h_dq[5] h_dq[4] h_dq[3] gnd_io2 h_procclock vcc_core1 gnd_core1 sys_clk h_dq[2] h_dq[1] h_csn h_dq[0] h_rwn h_wait h_irqn aud_clk pcm_dclk_in pcm_wclk_in v dda v ssa biasin agcinp adcrefl vcc_io7 gnd_io7 d_dq[13] d_dq[2] d_dq[12] gnd_io5 d_dq[3] d_dq[11] d_dq[4] d_dq[10] d_dq[9] d_dq[6] vcc_io4 d_dq[8] d_dq[7] d_ldqm d_udqm d_dq[5] d_clk vcc_core2 gnd_core2 gnd_io4 d_casn d_rasn d_wen d_addr[11] d_addr[12] d_addr[9] vcc_io3 d_addr[13] d_addr[8] d_addr[10] d_addr[7] d_addr[0] d_addr[6] gnd_io3 d_addr[1] d_addr[5] d_addr[2] d_addr[4] 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 90 89 88 87 86 85 84 83 82 81 100 101 102 99 98 97 96 95 94 93 92 91 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 120 119 118 117 116 115 114 113 112 111 128 127 126 125 124 123 122 121 110 109 108 107 106 105 104 103 dsd_pcm_9 dsd_pcm_10 vcc_io6 dsd_pcm_8 dsd_pcm_7 dsd_pcm_6 dsd_pcm_5 dsd_pcm_4 gnd_io6 dsd_pcm_3 h_a[2] h_a[3] h_a[4] h_a[5] h_a[6] h_a_sel resetn dsd_pcm_11 dsd_pcm_2 dsd_pcm_1 dsd_pcm_0 d_dq[15] vcc_io5 d_dq[0] d_dq[14] d_dq[1] ude_req data_req be_dat(1) be_dat(2) be_dat(3) be_dat(4) be_dat(5) be_dat(6) be_dat(7) trst pcm_celf_in pcm_leri_in pcm_lsrs_in b_flag/serr b_sync/sync b_wclk/senb b_data/be_dat(0) b_bclk/sdclk tms vcc_io2 tdo tdi tck h_sel[0] h_sel[1] d_addr[3]
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 8 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 6.2 pin description table 2: pin description symbol pin type [1] description h_a[1] 1 in address bus h_dq[15] 2 i/o10 data bus h_dq[14] 3 i/o10 data bus gnd_io1 4 gnd_io gnd i/o pads h_dq[13] 5 i/o10 data bus h_dq[12] 6 i/o10 data bus h_dq[11] 7 i/o10 data bus h_dq[10] 8 i/o10 data bus h_dq[9] 9 i/o10 data bus vcc_io1 10 vcc_io v cc i/o pads h_dq[8] 11 i/o10 data bus h_dq[7] 12 i/o10 data bus h_dq[6] 13 i/o10 data bus h_dq[5] 14 i/o10 data bus h_dq[4] 15 i/o10 data bus h_dq[3] 16 i/o10 data bus gnd_io2 17 gnd_io gnd i/o pads h_procclock 18 in host processor emi interface clock vcc_core1 19 vcc_core core supply voltage gnd_core1 20 gnd_core core ground sys_clk 21 in system clock h_dq[2] 22 i/o10 data bus h_dq[1] 23 i/o10 data bus h_csn 24 in host chip select; active low h_dq[0] 25 i/o10 data bus h_rwn 26 in read = 1; write = 0 h_wait 27 o10 wait signal h_irqn 28 o10 interrupt request; active low aud_clk 29 in dsd audio clock pcm_dclk_in 30 in pcm data clock pcm_wclk_in 31 in pcm word clock v dda 32 vddco v dd of adc v ssa 33 vssco v ss of agc and adc; connected to substrate biasin 34 apio bias current input agcinp 35 apio agc positive input signal; hf in adcre? 36 apio adc decoupling vcc_io7 37 vcc_io v cc i/o pads gnd_io7 38 gnd_io gnd i/o pads pcm_celf_in 39 in pcm data center or lfe
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 9 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. pcm_leri_in 40 in pcm data left or right pcm_lsrs_in 41 in pcm data left or right surround b_flag/serr 42 in i 2 s-bus ?ag (edc ?ag) b_sync/sync 43 in sector sync or absolute time sync b_wclk/senb 44 in i 2 s-bus word clock or ude data sense from host b_data/be_dat(0) 45 in i 2 s-bus data or lsb data of parallel interface b_bclk/sdclk 46 in i 2 s-bus bit clock ude_req 47 in host request data from front-end; routed via the SAA7893hl data_req 48 o10 data request for ude be_dat(1) 49 in front-end parallel data interface be_dat(2) 50 in front-end parallel data interface be_dat(3) 51 in front-end parallel data interface be_dat(4) 52 in front-end parallel data interface be_dat(5) 53 in front-end parallel data interface be_dat(6) 54 in front-end parallel data interface be_dat(7) 55 in front-end parallel data interface trst 56 in1 boundary scan reset tms 57 in1 boundary scan mode select vcc_io2 58 vcc_io v cc i/o pads tdo 59 o10 output tdi 60 in1 boundary scan data input tck 61 in boundary scan clock h_sel[0] 62 in host select signals: sad16, mad16 and sad08 h_sel[1] 63 in host select signals: sad16, mad16 and sad08 d_addr[3] 64 o10 sdram address bus d_addr[4] 65 o10 sdram address bus d_addr[2] 66 o10 sdram address bus d_addr[5] 67 o10 sdram address bus d_addr[1] 68 o10 sdram address bus gnd_io3 69 gnd_io gnd i/o pads d_addr[6] 70 o10 sdram address bus d_addr[0] 71 o10 sdram address bus d_addr[7] 72 o10 sdram address bus d_addr[10] 73 o10 sdram address bus d_addr[8] 74 o10 sdram address bus d_addr[13] 75 o10 sdram address bus vcc_io3 76 vcc_io v cc i/o pads d_addr[9] 77 o10 sdram address bus table 2: pin description continued symbol pin type [1] description
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 10 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. d_addr[12] 78 o10 sdram address bus d_addr[11] 79 o10 sdram address bus d_wen 80 o10 read or write d_rasn 81 o10 row address select; active low d_casn 82 o10 column address select; active low gnd_io4 83 gnd_io gnd i/o pads gnd_core2 84 gnd_core core ground vcc_core2 85 vcc_core core supply voltage d_clk 86 o10 clock signal needed for sdram d_dq[5] 87 i/o10 data bus d_udqm 88 o10 dq mask enable (upper) d_ldqm 89 o10 dq mask enable (lower) d_dq[7] 90 i/o10 data bus d_dq[8] 91 i/o10 data bus vcc_io4 92 vcc_io v cc i/o pads d_dq[6] 93 i/o10 data bus d_dq[9] 94 i/o10 data bus d_dq[10] 95 i/o10 data bus d_dq[4] 96 i/o10 data bus d_dq[11] 97 i/o10 data bus d_dq[3] 98 i/o10 data bus gnd_io5 99 gnd_io gnd i/o pads d_dq[12] 100 i/o10 data bus d_dq[2] 101 i/o10 data bus d_dq[13] 102 i/o10 data bus d_dq[1] 103 i/o10 data bus d_dq[14] 104 i/o10 data bus d_dq[0] 105 i/o10 data bus vcc_io5 106 vcc_io v cc i/o pads d_dq[15] 107 i/o10 data bus dsd_pcm_0 108 o10 6-channel data output dsd_pcm_1 109 o10 6-channel data output dsd_pcm_2 110 o10 6-channel data output dsd_pcm_3 111 o10 6-channel data output gnd_io6 112 gnd_io gnd i/o pads dsd_pcm_4 113 o10 6-channel data output dsd_pcm_5 114 o10 6-channel data output dsd_pcm_6 115 o10 6-channel clock/control dsd_pcm_7 116 o10 6-channel clock/control dsd_pcm_8 117 o10 2-channel clock/control vcc_io6 118 vcc_io v cc i/o pads table 2: pin description continued symbol pin type [1] description
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 11 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. [1] explanation of input and output ports: in: digital input port; all dedicated inputs are ttl tolerant. in1: digital input port with internal pull-up resistor. i/o10: bidirectional port with 10 ns slew rate. o10: 3-state (in test mode) output port with 10 ns slew rate. apio: analog input port. vddco: analog v dd port (1.8 v). vssco: analog v ss port. gnd_io: ground for i/o pads. vcc_io: v cc for i/o pads (3.3 v). gnd_core: ground for core. vcc_core: v cc for core (1.8 v). 7. interfaces 7.1 host interface different types of host busses are supported: ? separate address/data bus with 16-bit data bus (3 different modes) ? multiplexed address/data bus with 16-bit data bus (2 different modes) ? separate address/data bus with 8-bit data bus (1 mode). the host interface type is set via the dedicated pins h_sel and sys_clk. the SAA7893hl has a dedicated interrupt output pin. 7.2 front-end interface 7.2.1 data input interface the SAA7893hl supports three different front-end interfaces which are selectable via the host interface: ? i 2 s-bus interface: the front-end interface is in essence an i 2 s-bus interface and therefore, it has to conform to the i 2 s-bus speci?cation. ? fec interface dsd_pcm_10 119 o10 2-channel data output dsd_pcm_9 120 o10 2-channel clock or control dsd_pcm_11 121 o10 2-channel data output resetn 122 in asynchronous reset; active low h_a_sel 123 in address select h_a[6] 124 in address bus h_a[5] 125 in address bus h_a[4] 126 in address bus h_a[3] 127 in address bus h_a[2] 128 in address bus table 2: pin description continued symbol pin type [1] description
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 12 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. ? parallel interface (ude data interface part): a parallel front-end interface with a handshake protocol. 7.2.2 analog hf input the analog hf input, coming from the optical pickup unit, is also fed to the SAA7893hl to extract the copy protection information psp. 7.3 audio interface 7.3.1 audio input the audio input is a 6-channel pcm-i 2 s input. 7.3.2 dac interface the audio output is a 6-channel output and a separate stereo output. both outputs can be set in dsd and in pcm-i 2 s mode. 7.4 sdram interface the sdram interface forms a glueless interface to one 64 mbit sdram device. supported devices are only pc100 compliant or faster sdram devices: ? organization: 64 mbit (1m 16 4 banks) ? refresh period: 4096 cycles per 64 ms ? clock frequency: f clk 3 100 mhz ? refresh cycle: t rcar 70 ns ? command period: t rc 70 ns. 7.5 clock and reset input different processing clocks are needed in the SAA7893hl: ? sys_clk: system clock for data processing part; frequency can be between 27 and 35 mhz; see figure 6 and ta b l e 3 ? aud_clk: audio clock reference; can be 256/384/512/768 f s (f s = 44.1 to 48 khz); see figure 7 and ta b l e 4 ? proc_clk: host processor clock (only used in sad16_01/02 mode) ? b_bclk: front-end bit/byte clock. it is not required that these clocks are locked. resetn is an asynchronous reset and should be kept low for at least 10 periods of sys_clk.
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 13 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 7.5.1 system clock (sys_clk) de?nitions 7.5.2 audio clock (aud_clk) de?nitions 7.6 test inputs standard bst functionality is provided. device data: version: b0010 fig 6. sys_clk characteristics mdb146 t r t f t clk(l) t clk t clk(h) table 3: de?nitions of sys_clk symbol parameter conditions min max unit t clk clock cycle time clock frequency from 27 to 35 mhz 28.5 37.4 ns t clk(l) clock time low 11.4 22.4 ns t clk(h) clock time high 11.4 22.4 ns t f fall time -4 ns t r rise time -4 ns d clk clock duty cycle 40 60 % fig 7. aud_clk characteristics mdb146 t r t f t clk(l) t clk t clk(h) table 4: de?nitions of aud_clk symbol parameter conditions min max unit t clk clock cycle time clock frequency from 256 44.1 khz to 768 48 khz 27 88.6 ns t clk(l) clock time low 10.8 53.1 ns t clk(h) clock time high 10.8 53.1 ns t f fall time -4 ns t r rise time -4 ns d clk clock duty cycle 40 60 %
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 14 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. manufacturer id: b000 0001 0101 part no: b0011 0101 0110 0100. 8. host interface 8.1 general description the SAA7893hl is capable to communicate with the hosts (families) via their own busses as given in ta b l e 5 . the type of host is selected via two input pins h_sel[1] and h_sel[0] and the proc_clk signal. in ta b l e 6 the settings for the different host modes are given with the expected input clock(s). in all modes the range of the required internal system clock is between 27 and 35 mhz. the pin mapping in the different modes is shown in ta b l e 7 . table 5: host communications name description sad16_01 separate address/data on 16-bit data bus with wait signal, based on proc_clk sad16_02 separate address/data on 16-bit data bus with wait signal, based on sys_clk and proc_clk sad16_03 separate address/data on 16-bit data bus without wait signal mad16_01 multiplexed address/data on 16-bit data bus mode 01 mad16_02 multiplexed address/data on 16-bit data bus mode 02 sad08 separate address/data on 8-bit data bus table 6: clock selection h_sel[1:0] mode external provided clocks internal used system clock sys_clk proc_clk 00 sad16_01 no yes proc_clk/2 10 sad16_02 yes yes sys_clk 01 sad16_03 yes logic 1 sys_clk 11 mad16_01 yes logic 0 sys_clk 11 mad16_02 yes logic 1 sys_clk 01 sad08 yes logic 0 sys_clk table 7: host communication data mapping SAA7893hl name type sad16_01; sad16_02 sad08 mad16_01 mad16_02 sad16_03 h_a_sel in cpu_a(7) a(11) ale ale la(7) h_a[3:1] in cpu_a(4:1) a(3:1) la(2:0) addr[3:1] la(3:1) h_a[4] in cpu_a(4:1) a(4) la(3) n.c. la(4) h_a[6:5] in cpu_a(6:5) a(6:5) ad(21:20) n.c. la(6:5) h_dq[7:0] i/o cpu_d(7:0) d(7:0) ad(11:4) data(7:0) ld(7:0)
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 15 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. the internal SAA7893hl address is differently composed in the different modes. 8.2 sad16_01/02 mode reading and writing is always done on 16 bits (hword) base. to save physical pins on the SAA7893hl, the data bus is used to write the 16 msb address bits, hereafter called the base address into the SAA7893hl. therefore, to access an address inside the SAA7893hl ?rst these 16 msb bits of the address must be written as a base address for the SAA7893hl indicated by the h_a_sel line. pin h_a_sel can be mapped to a physical address pin of the host device. h_dq[11:8] i/o cpu_d(11:8) a(10:7) ad(1512) data(11:8) ld(11:8) h_dq[12] i/o cpu_d(12) n.c. ad(16) data(12) ld(12) h_dq[13] i/o cpu_d(13) asn ad(17) data(13) ld(13) h_dq[14] i/o cpu_d(14) dsn ad(18) data(14) ld(14) h_dq[15] i/o cpu_d(15) a(0) ad(19) data(15) ld(15) h_irqn o irqn irqn irqn irqn irqn h_procclock in cpu_procclk logic 0 logic 0 logic 1 logic 1 sys_clk in n.c.; sysclk pci-clk sclk sys_clk sys_clk h_rwn in cpu_rwn r/wn rd_ rd_ rd_ h_waitn o cpu_wait dsackn ack hdtackn n.c. h_csn in cpu_csn cs xio csn csn h_sel[0] in 0 logic 1 logic 1 logic 1 logic 1 h_sel[1] in logic 0: mode 1; logic 1: mode 2 logic 0 logic 1 logic 1 logic 0 table 7: host communication data mapping continued SAA7893hl name type sad16_01; sad16_02 sad08 mad16_01 mad16_02 sad16_03 fig 8. write to or read from the SAA7893hl. a(6:1) d(15:0) indication of an access to the base address write base address fur_base = a(22:7) write/read on SAA7893hl address locations fur_a[22:1] = fur_base&a(6:1) a(22:7) h_csn h_rwn h_a_sel h_a[6:1] h_dq[15:0] mce038 d(15:0) a(6:1)
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 16 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. in figure 8 the principle of ?rst writing the base address indicated by h_a_sel is here visualized. pin h_a_sel is mapped on address pin h_a[7] of the host. the timing is, of course, not to scale. when the base address is written, multiple accesses can be done whereby the different lsb addresses are mapped on pins h_a[6:1]. in this way a burst of 64 hwords can be read or written to the same address. the 16 bits base address can be read when h_a_sel is logic 1 and the signal h_rwn indicates a read operation. remark: the h_waitn signal is synchronized to h_procclock (pin 18). so it depends on the host used which h_procclock is provided. when the host can accept an asynchronous h_waitn signal, the clock signal connected to the sys_clk input (pin 21) can also be used as the clock signal to the h_procclock input. 8.2.1 write mode: minimum cycle fig 9. timing diagram of writing registers with no wait cycles. mbl622 h_csn h_rwn h_dq[15:0] h_a[6:1] h_a_sel h_waitn t tot t su t h table 8: timing numbers of writing registers with no wait cycles symbol parameter min typ max unit t tot total csn time 14 - - sys_clk t su set-up time from cs to host control/address lines --30ns t h hold time from cs to host control/address lines 0 - - ns
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 17 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 8.2.2 read mode: minimum cycle 8.2.3 write mode: cycles extended using wait protocol fig 10. timing diagram of reading registers with no wait cycles. mbl633 h_csn h_rwn h_a[6:1] h_a_sel h_dq[15:0] h_waitn t tot t su t h t h(d) t set t tri data undefined z z table 9: timing numbers of reading registers with no wait cycles symbol parameter conditions min typ max unit t tot total csn time 14 - - sys_clk t su set-up time from cs to host control/address lines 0 - 30 ns t h hold time from cs to host control/address lines maximum time is not needed; can be forever 0--ns t tri time that data bus is set from 3-state to output 1 - 3 sys_clk t set time that data is valid before cs is set to logic 1 60 - - ns t h(d) hold time from cs to data bus 0 - - ns fig 11. timing diagram of writing registers with wait cycles. mbl635 h_csn h_rwn h_waitn t tot t su t h t wt(en) t wt(st) t wt h_dq[15:0] h_a[6:1] h_a_sel
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 18 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. [1] when the SAA7893hl sad16 interface is programmed to generate always a h_wait signal, the minimum time will be 2 sys_clk cycles and the maximum time will be 3 sys_clk cycles. 8.2.4 read mode: cycles extended using wait protocol table 10: timing numbers of writing registers with wait cycles symbol parameter conditions min typ max unit t tot total csn time 14 - - sys_clk t su set-up time from cs to host control/address lines 0 - 30 ns t h hold time from cs to host control/address lines 0 - - ns t wt active time of h_wait when pi registers are accessed speed is dependent on load on pi-bus 3 8 11 sys_clk active time of h_wait when external sdram is accessed speed is dependent on load on pi-bus 3 11 17 sys_clk t wt(st) time from cs until wait becomes active 5 [1] -6 [1] sys_clk t wt(en) time h_wait inactive until cs becomes inactive 10 - - ns fig 12. timing diagram of reading registers via pi-bus. mbl636 h_csn h_rwn h_a[6:1] h_a_sel h_dq[15:0] h_waitn t tot t su t h t h(d) t set t tri data undefined z z t wt(en) t wt(st) t wt table 11: timing numbers of reading registers via pi-bus symbol parameter conditions min typ max unit t tot total csn time 14 [1] - - sys_clk t su set-up time from cs to host control/address lines 0 - 30 ns t h hold time from cs to host control/address lines 0 - - ns t wt active time of h_wait when pi registers are accessed speed is dependent on load on pi-bus 3 8 11 sys_clk active time of h_wait when external sdram is accessed speed is dependent on load on pi-bus 3 11 17 sys_clk t wt(st) time from cs until wait becomes active 5 [2] -6 [2] sys_clk
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 19 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. [1] when the SAA7893hl sad16 interface is programmed to generate always a h_wait signal of at least 7 sys_clk cycles, then it is no longer required that the minimum time of t tot is 14 sys_clk cycles. the data at the h_dq output is always available at the negative edge of the h_wait signal. the host can deactivate the h_cs signal after the negative edge of the h_wait signal and when it has read the data at the h_dq lines. when a h_wait signal is always generated then the timing diagrams in figure 9 and figure 10 are no longer applicable. [2] when the SAA7893hl sad16 interface is programmed to generate always a h_wait signal, the minimum time will be 2 sys_clk cycles and the maximum time will be 3 sys_clk cycles. 8.2.5 host interface connection 8.3 sad16_03 mode to save physical pins on the SAA7893hl, the data bus is used to write the 16 msb address bits, hereafter called the base address, into the SAA7893hl. therefore, to access an address inside the SAA7893hl ?rst this 16 msb bits of the address must be written as a base address for the SAA7893hl indicated by the h_a_sel line. pin h_a_sel can be mapped to a physical address pin of the host device. t wt(en) time from h_wait negative slope to data set-up - - 0 ns t tri time that data bus is set from 3-state to output 1 - 3 sys_clk t set time that data is valid before cs is set to logic 1 30 - - ns t h(d) hold time from cs to h_data bus 0 - - ns table 11: timing numbers of reading registers via pi-bus continued symbol parameter conditions min typ max unit fig 13. host interface connection. mce039 h_rwn cpu_rw ce2n cpu_wait cpu_addr(7) cpu_addr(6:1) cpu_addr(15:0) cpu_procclk irq_x h_csn h_wait 27 24 26 h_a_sel 123 h_a[6:1] 124, 125, 126, 127, 128, 1 h_procclk 18 sys_clk 21 gnd_io h_sel[0] 62 gnd_io h_sel[1] 63 gnd_io 28 h_dq[15:0] h_irqn 2, 3, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 22, 23, 25 10 k w SAA7893hl sad16_01 mode
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 20 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. in figure 14 the principle of ?rst writing the base address indicated by h_a_sel is here visualized. pin h_a_sel is mapped on address pin h_a[7] of the host. the timing is of course not to scale. when the base address is written, multiple accesses can be done whereby the different lsb addresses are mapped on pins h_a[6:1]. in this way a burst of 64 hwords can be read or written to the same address. the 16 bits base address can be read when h_a_sel is logic 1 and the signal h_rwn indicates a read operation. in sad16_03 mode there is in principle no handshake available. therefore, to read data a double read must be done. fig 14. write to or read from the SAA7893hl. a(6:1) d(15:0) indication of an access to the base address write base address fur_base = a(22:7) write/read on SAA7893hl address locations fur_a[22:1] = fur_base&a(6:1) a(22:7) h_csn h_rwn h_a_sel h_a[6:1] h_dq[15:0] mce038 d(15:0) a(6:1)
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 21 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 8.3.1 read mode first the 16 bits of the base address are set indicated by the h_a_sel line. then a read access is started. in sad16_03 mode there is no handshake line on which the SAA7893hl can indicate that internal read operation is ready. therefore, to be sure that the requested data is read correctly, an extra read is needed indicated by the h_a_sel line. in this read the data is presented as read by the previous read access. the maximum time that the host must wait before this extra read is started is approximately 30 sys_clk cycles. if in this time a new access is activated this access can be lost. fig 15. read from the SAA7893hl. a(6:1) t wt undefined indication of an access to the base address write base address fur_base = a(22:7) data is read indicated by h_a_sel read 'indication' on SAA7893hl address locations fur_a[22:1] = fur_base&a(6:1) a(22:7) h_csn h_rwn h_a_sel h_a[6:1] h_dq[15:0] mce040 d(15:0) undefined
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 22 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 8.3.2 write mode when a write operation is issued the same wait time t wt must be taken into account before a next access may start, but here no double write has to be done. 8.3.3 writing of base address fig 16. write to the SAA7893hl. a(6:1) t wt undefined indication of an access to the base address write base address fur_base = a(22:7) write on SAA7893hl address locations fur_a[22:1] = fur_base&a(6:1) a(22:7) d(15:0) h_csn h_rwn h_a_sel h_a[6:1] h_dq[15:0] mce041 fig 17. timing diagram of writing the base address. h_csn h_rwn h_a_sel h_a[6:1] h_dq[15:0] address[22:7] undefined mce042 t wt t su(rw) t su(ad) t h t tot
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 23 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 8.3.4 writing data to the SAA7893hl table 12: timing numbers of base address writing symbol parameter conditions min max unit t tot total low time of h_csn 270 - ns t wt wait time before next cycle may start if in this time a new cycle is started, the new access cycle could be neglected 100 - ns t su(rw) set-up time of h_rwn - 0 ns t su(ad) set-up time for address - 10 ns fig 18. writing data to the SAA7893hl. h_csn h_rwn h_a_sel h_a[6:1] h_dq[15:0] data[15:0] address[6:1] mce043 t wt t su(rw) t su(ad) t h t tot table 13: timing numbers of writing data symbol parameter conditions min max unit t tot total low time of h_csn 270 - ns t wt wait time before next cycle may start if in this time a new cycle is started, the new access cycle could be neglected 700 - ns t su(rw) set-up time of h_rwn - 0 ns t su(ad) set-up time for address - 10 ns t h hold time of h_rwn/address/data with respect to h_csn 0- ns
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 24 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 8.3.5 reading data from the SAA7893hl fig 19. reading data from the SAA7893hl. h_csn h_rwn h_a_sel h_address(6:1) h_data don't care undefined data z z h_a(6:1) mce044 t tot t wt t tot t su(ad) t su(rw) t d(tri) t h(d) t h table 14: timing numbers of reading data symbol parameter conditions min max unit t tot total low time of h_csn 270 - ns t wt wait time before next cycle may start if in this time a new cycle is started, the new access cycle could be neglected 700 - ns t su(rw) set-up time of h_rwn - 0 ns t su(ad) set-up time for address - 10 ns t tri time that data bus is enabled time dependent on system clock 1 3 sys_clk
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 25 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 8.3.6 host interface connection 8.4 mad16_01 mode data communication is here always done on a 16-bit data bus. the address is mapped on 6 separate address pins and 16 address/data pins of the SAA7893hl. therefore, in this mode the complete address is transferred directly in each access cycle. in ta b l e 7 the internal SAA7893hl address is mapped as follows to the SAA7893hl pins: fur_h_a[22:1] = h_a[6:5] & h_dq[15:0] & h_a[4:1]. this address mapping is the default setting, the following address is also possible: fur_h_a[22:1] = h_a[6:1] & h_dq[15:0]. the system clock provided in the mad16_01 mode must be synchronized to the host interface timing. fig 20. host interface connection. mce045 h_rwn rd_ csn la(7) la(6:1) ld(15:0) irq_x h_csn h_wait 27 n.c. 24 26 h_a_sel 123 h_a[6:1] 124, 125, 126, 127, 128, 1 h_procclk 28 sys_clk sys_clk or video clock 21 vcc_io vcc_io h_sel[0] 62 h_sel[1] 63 gnd_io 18 h_dq[15:0] h_irqn 2, 3, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 22, 23, 25 SAA7893hl sad16_03 mode
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 26 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 8.4.1 write mode: minimum cycle fig 21. timing diagram writing to the SAA7893hl. sys_clk h_csn h_a_sel h_rwn h_wait addr addr data h_dq[15:0] h_a[6:1] mbl637 t dw t rd t su t h t tot table 15: timing numbers of writing registers symbol parameter min max unit t tot total h_csn time 8 - sys_clk t su set-up time h_a_sel 5 - ns t h hold time of h_a_sel with respect to sys_clk 5 - ns t rd time h_rwn can change from h_csn signal - 1 sys_clk t su(d) data set-up time after h_csn 0 1 sys_clk
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 27 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 8.4.2 read mode: minimum cycle fig 22. timing diagram reading from the SAA7893hl. sys_clk h_csn h_a_sel h_rwn h_wait addr addr data h_dq[15:0] h_a[6:1] mbl638 t dr t rd t su t h table 16: timing numbers of reading registers symbol parameter conditions min max unit t su set-up time h_a_sel 5 - ns t h hold time of h_a_sel with respect to sys_clk 5- ns t rd time h_rwn can change from h_csn signal - 1 sys_clk t dr data set-up time after csn time dependent on system clock used 6 8 sys_clk t dc data hold time before csn not important data is sample after detecting h_csn = logic 0 --ns
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 28 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 8.4.3 write mode: cycles extended using wait protocol fig 23. timing diagram writing to the SAA7893hl (with wait cycles). sys_clk h_csn h_a_sel h_rwn h_wait addr addr data h_dq[15:0] h_a[6:1] mbl639 t dw1 t dw2 t wt t rd t su t h t tot table 17: timing numbers of writing registers (with wait cycles) symbol parameter conditions min max unit t tot total h_csn time 8 - sys_clk t su set-up time h_a_sel 5 - ns t h hold time of h_a_sel with respect to sys_clk 5- ns t rd time h_rwn can change from h_csn signal - 1 sys_clk t dw1 data set-up time after h_csn time dependent on system clock used 1 3 sys_clk t dw2 time h_wait is activated after h_csn is activated dependent on SAA7893hl settings 2 6 sys_clk t wt total time wait can be active 2 24 sys_clk
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 29 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 8.4.4 read mode: cycles extended using wait protocol fig 24. timing diagram reading from the SAA7893hl (with wait cycles). sys_clk h_csn h_a_sel h_rwn h_wait addr addr data h_dq[15:0] h_a[6:1] mbl640 t dw t wt t ac t rd t su t h table 18: timing numbers of reading registers (with wait cycles) symbol parameter min max unit t tot total h_csn time 8 - sys_clk t su set-up time h_a_sel 5 - ns t h hold time of h_a_sel with respect to sys_clk 5- ns t rd time h_rwn can change from h_csn signal - 1 sys_clk t dw time h_wait is activated after h_csn is activated dependent on SAA7893hl settings 2 5 sys_clk t wt total time wait can be active 2 24 sys_clk t ac data active until h_csn is deactivated 1 - sys_clk
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 30 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 8.4.5 host interface connection 8.5 mad16_02 mode in the mad16_02 mode there is a 16-bit combined address/data bus and a dedicated 3-bit address bus. fig 25. host interface connection. mce046 h_rwn xio_x xio_x vcc_io ale x_ack ad(21:16) irq_x sclk h_csn h_wait 27 24 26 h_a_sel 123 sys_clk 21 h_irqn 28 h_procclk 18 gnd_io h_sel[0] 62 vcc_io h_sel[1] 63 vcc_io h_a[6:1] 124, 125, 126, 127, 128, 1 ad(15:0) h_dq[15:0] 2, 3, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 22, 23, 25 10 k w SAA7893hl mad16_01 mode
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 31 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. the multiplexing of the address/data pins is done as a regular host communication, meaning that during a read or write the host must automatically generate the timing according to figure 26 . it is not needed that the provided system clock is a synchronous clock with respect to the h_a_sel line. 8.5.1 write mode fig 26. principle read. h_csn h_a_sel h_rwn h_a[3:1] h_waitn h_dq[15:0] undefined ha[3:1] ha[22:20] zz data[15:0] ha[19:4] mce047 fig 27. timing diagram writing to the SAA7893hl. h_csn h_a_sel h_rwn h_a[3:1] h_waitn h_dq[15:0] ha[3:1] ha[22:20] data[15:0] ha[19:4] mce048 t h(ad) t wt t dw1 t tot t su t h(cs)
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 32 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 8.5.2 read mode table 19: timing numbers of mad16_02 write symbol parameter min max unit t tot total low time of h_csn 300 + t wt -ns t h hold time of address/data with respect to h_a_sel 10 - ns t dw1 wait time until h_wait is activated 2 5 sys_clk t wt time of h_wait signal 2 24 sys_clk t su set-up time of h_rwn/address with respect to h_csn -10ns fig 28. timing diagram reading from the SAA7893hl. h_csn h_a_sel h_rwn h_a[3:1] h_waitn h_dq[15:0] undefined ha[3:1] ha[22:20] z data[15:0] ha[19:4] mce049 t h t tri t set(d) t wt t dw1 t tot t su table 20: timing numbers of mad16_02 read symbol parameter min typ max unit t tot total h_csn time 8 + t wt --ns t su set-up time of address/data/h_rwn with respect to h_csn --0ns t h hold time of address with respect to h_a_sel falling edge 10--ns t dw1 time h_wait is activated after h_csn is activated - - 4 sys_clk
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 33 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 8.5.3 host interface connection 8.6 sad08 mode here the reading and writing is always done on 8-bit. from pin mapping it can be seen that the byte indication is done via bit a(0) which is mapped on h_dq(15) of the SAA7893hl. the internal SAA7893hl communication stays on 16-bit. therefore, the host interface block translates the 8 bits external communication to the 16 bits internal. to save physical pins on the SAA7893hl device, the data bus and 4 address bits are used to write the 12 msb address bits, hereafter called the base address, into the SAA7893hl device. therefore, to access an address inside the SAA7893hl ?rst this 12 msb bits of the address must be written as a base address for the SAA7893hl indicated by the h_a_sel line. pin h_a_sel can be mapped to a physical address pin of the host. t tri time data bus becomes active after h_csn - 2 - sys_clk t set(d) time data available with respect to h_wait signal 15--ns t wt time h_wait can be active 2 - 24 sys_clk table 20: timing numbers of mad16_02 read continued symbol parameter min typ max unit fig 29. host interface connection. mce050 h_rwn rd_ csn hdtackn ale n.c. addr(3:1) data(15:0) irq_x h_csn h_wait 27 24 26 h_a_sel 123 h_a[6:4] 124, 125, 126 h_a[3:1] 127, 128, 1 h_procclk 28 sys_clk sys_clk or video clock 21 vcc_io vcc_io vcc_io h_sel[0] 62 h_sel[1] 63 18 h_dq[15:0] h_irqn 2, 3, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 22, 23, 25 SAA7893hl mad16_02 mode
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 34 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 8.6.1 writing base address in figure 30 the writing of the base address and a hword to the host is given in sad08 mode. first, the 12 bits base address is written indicated by h_a_sel line. the SAA7893hl samples the base address on h_dq(7:0) and h_dq(11:8). after that the normal write operation is performed as explained in section 8.6.2 . 8.6.2 writing to the SAA7893hl a write to address n of 16 bits to the SAA7893hl will be translated to two byte accesses. first the lsb byte is written to address n [so a(0) = logic 0] and stored in cache. then the msb byte is written to address n+1 [so a(0) = logic 1]. when the SAA7893hl receives a write command at an odd address [a(0) = logic 1] always 16 bits are internally written whereby the hword is composed of lsb byte in cache and the msb byte received at present write command. the SAA7893hl can be set to big and little endian, whereby the described situation is the power-on state. byte read or write operations are not supported in sad08 mode. fig 30. base address writing. a(6:1) d(7:0) a(22:15) d(15:8) a(10:7) indication of an access to the base address write base address fur_base = a(22:11) write/read on SAA7893hl address locations fur_a[22:1] = fur_base&a(10:1) a(14:11) h_csn h_rwn h_a_sel h_a[6:1] h_dq[15] h_dq[7:0] h_dq[11:8] mce051 a(10:7) a(6:1) msb write/read lsb write/read
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 35 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 8.6.3 reading from the SAA7893hl when the lsb is read [a(0) = logic 0], the host interface will read an hword on the address location a(22:1). the lsb byte is set on the output bus and the read msb byte is stored internally. when a read action is now started whereby the msb byte is selected to read [a(0) = logic 1] the stored byte is available on the output independent on the other address bits a(22:1). fig 31. timing diagram sad08 write to SAA7893hl. address data sys_clk h_csn t h t su h_dq[13] h_dq[14] h_wait h_dq[7:0] h_dq[11:8] h_a[7:0] h_rwn mbl641 m clock cycles t h t d(as) t d t d(ds) table 21: timing numbers of sad08 write symbol parameter conditions min max unit t su set-up time from h_csn, h_rwn and h_dq(13) to sys_clk 5- ns t h hold time from clk to h_csn, h_rwn and h_dq(13) 5- ns t d(as) delay from h_csn to negative slope of h_dq(13) - 1 sys_clk t d(ds) delay from h_csn to negative slope of h_dq(14) and data - 2 sys_clk m number of clock cycles dependent on access type and traf?c on pi-bus 4 15 sys_clk t d delay from clk to dsackn 2 12 ns
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 36 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. fig 32. timing diagram sad08 read from the SAA7893hl. address data sys_clk h_csn t h t su h_dq[13] h_dq[14] h_wait h_dq[7:0] h_dq[11:8] h_a[7:0] h_rwn mbl623 n clock cycles t h t d t dat table 22: timing numbers of sad08 read symbol parameter conditions min max unit t su set-up time from h_csn, h_rwn and h_dq[13] to sys_clk 5ns t h hold time from clk to h_csn, h_rwn and h_dq[13] 5ns n number of clock cycles dependent on access type and traf?c on pi-bus. 5 20 sys_clk t d delay from clk to h_wait 2 12 ns t dat data available before h_wait is asserted -0 ns
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 37 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 8.6.4 host interface connection 8.7 interrupt the interrupt output is a low level interrupt which must be connected to the interrupt input of the dvd host. 9. front-end interface first the sacd sector structure is explained and how to connect the SAA7893hl in the different modes. for these different modes the interface timing ?gures will be given. the supported sector format interface is sketched in figure 34 . fig 33. host interface connection. mce052 h_rwn cpu_rw ce2n vcc_io xio_addr(11) cpu_wait xio_addr(10:7) xio_addr(6:1) as ds irq_x pci_clk xio_data(7:0) xio_addr(0) h_csn h_wait 27 24 26 h_a_sel 123 h_dq[15] 2 h_dq[14] 3 h_dq[11:8] 7, 8, 9, 11 h_dq[13] 5 sys_clk 21 h_irqn 28 h_procclk 18 gnd_io h_sel[0] 62 vcc_io h_sel[1] 63 gnd_io h_a[6:1] 124, 125, 126, 127, 128, 1 h_dq[7:0] 12, 13, 14, 15, 16, 22, 23, 25 10 k w SAA7893hl sad08 mode
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 38 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. the SAA7893hl supports a data input bit rate of maximal 40 mbits/s. the connections to the SAA7893hl in the different front-end modes are given in ta b l e 2 3 . [1] the n.c. input pins must be connected to v cc or gnd. 9.1 i 2 s-bus interface 9.1.1 input timing in figure 35 the functional input timing is given. note that b_sync, b_flag are sampled simultaneously with d11. since b_flag indicates the error in a byte, it is also sampled simultaneously with d3. the sampling moment during d11 for the high byte (d15 to d8), sampling moment d3 for the low byte (d7 to d0). fig 34. sacd sector format. header 12 2048 stored in vbr sector format 4 byte 0 to 11 edc byte 2060 to 2063 main data byte 12 to 2059 information byte 0 ied byte 4 to 5 number byte 1 to 3 cpsi mbl616 byte 6 to 11 id[31...24] id[23...0] table 23: connection of different front-end interfaces SAA7893hl name type i2s_mode fec parallel mode b_flag in i2s_err n.c. [1] serr b_sync in i2s_sync out_sync sync b_wclk in i2s_wclk out_dvalid senb b_bclk in i2s_bclk out_clk sdclk b_data in i2s_data out_data0 mpeg(0) be_dat(7:1) in n.c. [1] n.c. [1] mpeg(7:1) ude_req in n.c. [1] n.c. [1] ude_req data_req o n.c. n.c. req
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 39 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. when the b_sync signal is set to logic 1 between bit position d15 and d11 the SAA7893hl accepts this word as the start of a sector. the SAA7893hl does not perform edc checking on the main data, but is dependent on the b_flag. a sector is set to erroneous if b_flag is set to logic 1. 9.1.2 interface timing fig 35. front-end input timing. mbl617 b_data d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 i 2 s-bus half word d7 d6 d5 d4 d3 d2 d1 d0 b_bclk b_wclk b_sync b_flag fig 36. timing in i 2 s-bus interface. mbl624 b_bclk t su t h b_sync b_flag b_wclk b_data table 24: timing in i 2 s-bus interface symbol parameter min unit t su set-up time to rising edge of the clock 5 ns t h hold time after rising edge of the clock 5 ns
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 40 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 9.1.3 interface connection 9.2 ude data interface in the sa-mp the synchronous parallel mode is supported. there are three types of parallel data transfer modes supported: ? synchronous mode (see section 9.2.1 ) ? asynchronous mode: C handshake to enable data transfer C handshake for every byte transfer. not used input pins must be connected to v cc or gnd. fig 37. front-end interface connection. mce053 b_data 45 b_flag 42 b_sync 43 b_wclk 44 b_bclk 46 be_dat(7:1) 49-55 ude_req 47 open data_req 48 i2s_clk i 2 s-bus front-end ic i2s_wclk i2s_sync i2s_err i2s_dat SAA7893hl
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 41 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 9.2.1 parallel mode polarity of data_req, b_wclk, b_flag and b_sync is programmable. the ude transmitter must react on the data_req signal within 5 b_bclk cycles. the SAA7893hl samples the data on the positive slope of b_bclk when the b_wclk signal is active. when b_flag signal is active for one byte of the sector, the total sector will be treated as erroneous. the maximum clock frequency of b_bclk is 20 mhz. the data_req line generated by the SAA7893hl is synchronized to the internal sys_clk signal. therefore, the data_req line is asynchronous with respect to bclk line. fig 38. timing diagram for ude interface with level sync mode. b_bclk data_req b_wclk b_flag b_sync be_dat(7:0) sa_2059 sa_2060 sa_2061 empty empty empty sa_2062 sa_2063 sb_0 sb_1 sb_2 sb_3 empty sb_4 sb_5 sb_6 mce054 t clk(h) t su t su t clk(l) t h t h
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 42 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. polarity of data_req, b_wclk, b_flag and b_sync is programmable. fig 39. timing diagram for ude interface with sync edged triggered mode. b_bclk data_req b_wclk b_flag b_sync be_dat(7:0) sa_2059 sa_2060 sa_2061 empty empty empty sa_2062 sa_2063 sb_0 sb_1 sb_2 sb_3 empty sb_4 sb_5 sb_6 mce055 t su t su t h t h table 25: timing in synchronous parallel mode symbol parameter conditions min max unit t clk(h)(l) high/low time of the b_bclk signal maximum clock frequency of b_bclk is 20 mhz 20 - ns t su set-up time to rising edge of the clock data/control must be stable during t su before positive slope of b_bclk 10 - ns t h hold time after rising edge of the clock data/control must be kept at least during t h after positive slope of b_bclk 5- ns t o output delay from the clock 2 15 ns
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 43 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 9.2.2 interface connection 9.3 fec interface this is a serial interface for communication to a special front-end ic. the timing diagram of the fec interface is given in figure 41 . the ?rst bit of a sector is indicated by the sync signal; this is the msb bit of the ?rst byte of the header. the sector error indication is in fec mode indicated by two extra bytes at the end of the sector. this means that the sector length is increased to 2066 bytes. the indication of errors is as follows: ff = error; 00 = no error. fig 40. front-end interface connection. mce056 b_data be_dat(7:1) data_req ude_req 45 b_flag 42 b_sync 43 b_wclk 44 b_bclk 46 sdclk req 49-55 senb sync serr data sdclk ude front-end ic senb sync serr 48 47 req data SAA7893hl dvd back-end ic with ude fig 41. fec interface. mbl619 bclk/ ser_bclk be_dat(0)/ ser_data wclk/ ser_valid sync/ ser_sync bit 2 bit 1 bit 4 bit 3 bit 6 bit 5 bit 8 bit 7 bit 10 bit 9 bit 12 bit 11 bit 14 bit 13 bit 16 bit 15
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 44 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 9.3.1 timing 9.3.2 interface connection 10. hf input 10.1 general on every sacd disc a psp signal must be recorded. the player is only allowed to play a disc if a valid psp signal is detected. this psp key is recorded via a special mechanism in the efm signal on disc. the efm+ signal must be fed to the SAA7893hl as shown in figure 44 . fig 42. timing in fec interface. mbl624 b_bclk t su t h b_sync b_flag b_wclk b_data table 26: timing in fec interface symbol parameter min unit t su set-up time to rising edge of the clock 10 ns t h hold time after rising edge of the clock 5 ns fig 43. front-end interface connection. mce057 b_data 45 b_flag 42 gnd_io b_sync 43 b_wclk 44 b_bclk 46 be_dat(7:1) 49-55 ude_req 47 open data_req 48 ser_clk fec front-end ic ser_valid ser_sync ser_dat SAA7893hl
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 45 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. the detection of the psp key is dependent of the polarity of the efm+ signal. the sa-mp settings are that a pit on the disc must have a higher output voltage than the land. the efm+ input signal has no timing requirements with respect to the digital input of the front-end interface of the SAA7893hl. the SAA7893hl supports also an inversion of the efm+ signal. 10.2 hf input speci?cation the agc circuit must be able to handle the following signal characteristics of the hf input signal. the hf is ac-coupled via a capacitor of 10 nf to pin agcinp. the internal resistance of pin agcinp is 1 m w . fig 44. connection of efm+ input. agcinp efm + v dda 10 nf 100 nf 12 k w + 1.8 v v ssa mbl620 adcrefl biasin table 27: hf signal characteristics hf value remark input range 0.2 to 0.8 v (p-p) hf input voltage bandwidth 9 mhz front-end running on maximum speed needed for sacd table 28: signal connections pin name description agcinp hf output from pickup unit connected via a 10 nf couple capacitor biasin bias current; connect a 12 k w resistor to v ss (ground) adcre? reference voltage for internal resistor trap; decouple with 100 nf to v ss (ground) v ssa analog ground v dda 1.8 v analog power supply
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 46 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 10.3 hf-input application diagram 11. audio interfaces 11.1 audio input interface the pcm-i 2 s audio input signals can be either directly couple, without any processing to the dsd_pcm output lines, or further processed inside the SAA7893hl. when directly coupled, only a combinatorial delay must be taken into account; no dependency on any clock signal (see section 11.1.1 ). the input signal characteristics, when audio processing must be performed, are given in section 11.1.2 . 11.1.1 audio input directly coupled when no processing is done inside the SAA7893hl with respect to the i 2 s-pcm input stream, this input stream is sent via a multiplexer to the i 2 s-bus output paths. so no clocking is done on this signal, meaning that also no locked audio clock needs to be present. fig 45. efm input interface connection. agcinp efm + (0.2-0.8 v) v dda 10 nf 3 4.7 m f 35 32 33 36 34 100 nf 100 nf 12 k w + 1.8 v v ssa mce058 adcrefl SAA7893hl biasin fig 46. delay from input to output pin. mbl627 input pin output pin t d(as) table 29: timing numbers in pcm audio symbol parameter min typ max unit t d(as) asynchronous delay 8 13 18 ns
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 47 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 11.1.2 audio input with processing 11.1.3 interface connection 11.2 audio output interface the 6-channel outputs can be either dsd format or pcm-i 2 s format. the connections are given in ta b l e 3 1 . fig 47. audio i 2 s-bus input timing. msb right channel right surround lfe 16/24/32/48 clock cycles pcm_wclk_in pcm_dclk_in pcm_leri_in pcm_lsrs_in pcm_celf_in left channel left surround center 3 222 1 msb lsb 3 2 1 mbl628 t su t h 24 data bits t su t h table 30: timing numbers in pcm audio symbol parameter conditions min unit t su set-up time to rising edge to the pcm_dclk_in signal in pcm-i 2 s mode, the data is always outputted on the negative edge of the bit clock; so here data is sampled on positive edge of the clock 8ns t h hold time after rising edge of the pcm_dclk_in signal in pcm-i 2 s mode, the data is always outputted on the negative edge of the bit clock; so here data is sampled on positive edge of the clock 5ns fig 48. audio i 2 s-pcm input interface connection. mce059 pcm_celf_in 39 pcm_lsrs_in 41 pcm_leri_in 40 pcm_wclk_in 31 pcm_dclk_in 30 aud_clk 29 aud_clk_in dvd back-end ic audio clock 256/384/512/768 x f s i2s_clk i2s_wclk i2s_leri i2s_celfe i2s_isrs SAA7893hl
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 48 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. the SAA7893hl has 12 output lines: 8 lines are allocated for connection to a 6-channel dac and 4 are for connection to a 2-channel dac or a 75 hz reference signal. the dsd data on the mch output lines are outputted 6412 clocks after the positive edge of the 75 hz signal, if no additional post-processing is done. the sa-mp delivers extra ?exibility when connecting to different dac types, which can be: dsd only, pcm only or multi standard (dsd + pcm)]. in ta b l e 3 1 the signal allocation is given for the 6-channel output in dsd and in pcm-i 2 s mode. in ta b l e 3 2 the signal allocation is given for the dsd/pcm signals to be connected to the stereo dac. fig 49. sa-mp output line allocation. dsd_pcm_0 dsd_pcm_1 dsd_pcm_2 dsd_pcm_3 dsd_pcm_4 dsd_pcm_5 to 6-channel dac to 2-channel dac dsd_pcm_6 dsd_pcm_7 sa-mp dsd_pcm_8 dsd_pcm_9 dsd_pcm_10 dsd_pcm_11 mbl621 table 31: connection to a 6-channel dac output line pin number mode = dsd mode = pcm dsd_pcm_0 108 left channel l f +r f ; l s +r s ; c + lfe; 0 or 1; pcm data/word clock dsd_pcm_1 109 right channel l f +r f ; l s +r s ; c + lfe; 0 or 1; pcm data/word clock dsd_pcm_2 110 center channel l f +r f ; l s +r s ; c + lfe; 0 or 1; pcm data/word clock dsd_pcm_3 111 lfe channel l f +r f ; l s +r s ; c + lfe; 0 or 1; pcm data/word clock dsd_pcm_4 113 left surround l f +r f ; l s +r s ; c + lfe; 0 or 1; pcm data/word clock dsd_pcm_5 114 right surround l f +r f ; l s +r s ; c + lfe; 0 or 1; pcm data/word clock dsd_pcm_6 115 dsd clock or 0or1 pcm data/word clock dsd_pcm_7 116 dsd clock or 0or1 pcm data/word clock
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 49 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. both tables show that dsd has a ?xed allocation while pcm outputs are selectable. the i 2 s-bus bit stream, generated by the SAA7893hl decimation ?lter, is in the philips format as can be seen in the timing diagrams. the number of data bits is always 24. the wclk identi?cation is always active for 32 clocks for each left and right sample, except when the input clock is 384f s and the output sample frequency is 4f s ; then the wclk is 48 samples active. 11.2.1 dsd output remark: in this example timing of the aud_clk is 256 f s and dsd clock phase is set to logic 0. if phase is set to logic 1, the dsd_clk signal will be inverted. table 32: connection to a 4-channel dac output line pin number mode = dsd mode = pcm mode=75hz dsd_pcm_8 117 dsd clock pcm data/word clock 0 or 1 dsd_pcm_9 120 0 or 1 pcm data/word clock 0 or 1 dsd_pcm_10 119 left channel l f +r f ; 0 or 1 75 hz dsd_pcm_11 121 right channel l f +r f ; 0or1 0or1 table 33: serial bit clock frequency audio input clock i 2 s output wclk frequency dclk (data bit) frequency remark 256f s 2f s 128f s 4f s 256f s 384f s 2f s 128f s no symmetrical bit clock 4f s 384f s 48 clocks for a word identi?cation 512f s 2f s 128f s 4f s 256f s 768f s 2f s 128f s 4f s 256f s fig 50. audio i 2 s-bus output timing. mbl629 dsd_clk (= 64f s ) aud_clk dsd_pcm-data sample n sample n + 1 t d(o)
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 50 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 11.2.2 i 2 s-pcm generated by the SAA7893hl in figure 51 and figure 52 the timing diagrams are given when the internal pcm generator of the SAA7893hl generates the i 2 s-pcm output signals. table 34: timing numbers in dsd audio symbol parameter min max unit t d(o) output delay time with respect to the audio clock 4 20 ns fig 51. audio i 2 s-bus output timing in philips format. msb right channel right surround lfe 32 pcm_dclk_out clock cycles pcm_wclk_out pcm_dclk_out pcm_leri_out pcm_lsrs_out pcm_celf_out left channel left surround center 3 222 1 msb lsb 3 2 1 mbl630 t data 24 data bits t wclk fig 52. audio i 2 s-bus output timing in left justi?ed format. left channel left surround center 32 clock cycles right channel right surround lfe 3 222 1 msb lsb 3 2 1 mbl631 t data 24 data bits t wclk msb table 35: timing numbers for pcm-i 2 s output symbol parameter min max unit t wclk pcm_wclk_out timing with respect to negative edge of pcm_dclk_out - 10 +10 ns t data pcm_data_out timing with respect to negative edge of pcm_dclk_out - 10 +10 ns
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 51 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 11.3 audio output application diagrams 11.3.1 hybrid dac connection fig 53. hybrid dac interface connection. mce060 sdata_isrs m_x sclk wclk 113 sclk wclk sdata_ifrf m_x 114 m_x 111 sdata_celfe 110 m_x 109 sdata_ifrf 108 dsd_pcm_0 dsd_left/ i2s_lfrf dsd_clk/ i2s_dclk dsd_clk/ i2s_dclk '0'/ i2s_wclk '0'/ i2s_wclk dsd_left_sur/ i2s_lsrs dsd_left_mix/ i2s_lmrm dsd_right_mix/ '0' dsd_right_sur/ '0' dsd_right/ '0' dsd_centre/ i2s_celfe hybrid mca dac hybrid stereo dac mclk aud_clk mclk all slew rate controlled output pins (no serial resistors needed) audio clock dsd_pcm_1 dsd_pcm_2 dsd_pcm_3 dsd_pcm_4 dsd_pcm_5 116 115 dsd_pcm_6 dsd_pcm_7 117 dsd_pcm_8 119 121 29 120 dsd_pcm_9 dsd_pcm_10 dsd_pcm_11 SAA7893hl dsd_lfe/ '0'
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 52 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 11.3.2 dsd dac connection fig 54. dsd dac interface connection. mce061 dsd_ls dsd_rs sclk n.c. n.c. 113 dsd_clk dsd_left dsd_right 114 dsd_lfe 111 dsd_centre 110 dsd_right 109 dsd_left 108 dsd_pcm_0 dsd_left dsd_clk dsd_clk dsd_left_sur dsd_left_mix dsd_right_mix dsd_right_sur dsd_right dsd_centre dsd mca dac dsd stereo dac mclk aud_clk mclk audio clock dsd_pcm_1 dsd_pcm_2 dsd_pcm_3 dsd_pcm_4 dsd_pcm_5 116 115 dsd_pcm_6 dsd_pcm_7 117 dsd_pcm_8 119 121 29 120 dsd_pcm_9 dsd_pcm_10 dsd_pcm_11 SAA7893hl dsd_lfe
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 53 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 11.3.3 pcm dac connection fig 55. pcm dac interface connection. mce062 sdata_lsrs sclk wclk n.c. n.c. n.c. n.c. 113 sclk sdata_lfrf wclk 114 111 sdata_celfe 110 109 sdata_lfrf 108 dsd_pcm_0 i2s_lfrf i2s_dclk i2s_wclk i2s_dclk i2s_lsrs i2s_lmrm i2s_wclk i2s_celfe pcm mca dac pcm stereo dac mclk aud_clk mclk audio clock dsd_pcm_1 dsd_pcm_2 dsd_pcm_3 dsd_pcm_4 dsd_pcm_5 116 115 dsd_pcm_6 dsd_pcm_7 117 dsd_pcm_8 119 121 29 120 dsd_pcm_9 dsd_pcm_10 dsd_pcm_11 SAA7893hl
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 54 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 12. sdram interface 12.1 writing fig 56. sdram interface writing. active write address address data zzzz zzzz xx xx upper/lower byte precharge nop clk d_clk d_addr[13:0] d_dq[15:0] d_rasn d_casn d_wen d_udqm d_ldqm mbl632 t d t cmd t addr t data t dqm table 36: timing numbers of sdram interface writing symbol parameter conditions min max unit t d delay from clk to d_clk of sdram interface d_clk is clock of sdram 3 9 ns t cmd delay from clk to control signals 1 15 ns t addr delay from clk to address lines 1 15 ns t dqm delay from clk to d_udqm and d_ldqm signals 112ns t data delay from clk to data output signals 1 12 ns
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 55 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 12.2 reading fig 57. sdram interface reading. data to SAA7893hl active address address upper/lower byte read nop nop nop precharge nop clk d_clk d_addr[13:0] d_dq[15:0] d_rasn d_casn d_wen d_udqm d_ldqm mbl634 t d t cmd t addr t dqm t h t su table 37: timing numbers of sdram interface reading symbol parameter conditions min max unit t d delay from clk to d_clk of sdram interface d_clk is clock of sdram 3 9 ns t cmd delay from clk to control signals 1 15 ns t addr delay from clk to address lines 1 15 ns t dqm delay from clk to d_udqm and d_ldqm signals 112ns t su set-up time of data to clk 3 - ns t h hold time of data from clk 3 - ns
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 56 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 12.3 interface connection fig 58. sdram interface connection. mce063 ba1 75 ras_ 81 ba0 78 a(11:0) dq(15:0) dqmh 88 dqml 89 cs_ clk 86 we_ 80 cas_ 82 cke 64 mbit sdram +3.3 v d_dq[15:0] d_addr[11:0] d_addr[12] d_addr[13] d_rasn d_casn d_wen d_clk d_udqm d_ldqm SAA7893hl
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 57 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 13. power supply connections fig 59. power supply connections. mce064 10 vcc_io1 3.3 to 1.8 v convertor (lf18cd) 100 mhz coil gnd_io1 vcc_io7 gnd_io7 vcc_io2 gnd_io2 vcc_io3 gnd_io3 vcc_io4 gnd_io4 vcc_io5 gnd_io5 vcc_io6 gnd_io6 38 4 37 100 nf SAA7893hl 100 nf 17 58 100 nf 69 76 100 nf 83 92 100 nf 99 106 100 nf 100 nf 4.7 m f 100 nf 4.7 m f 4.7 m f 112 118 100 nf vcc_core1 gnd_core1 vcc_core2 gnd_core2 20 19 100 nf 3.3 v 84 85 100 nf v ssa v dda 33 32 100 nf 100 mhz coil 4.7 m f 3.3 to 1.8 v convertor (lf18cd) 100 nf 4.7 m f
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 58 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 14. software api 14.1 api provided by sa-mp table 38: api provided by sa-mp name description playback api nav_areaswitch switch sacd area nav_playtrack start playing at the index of the track nav_playattimecode start playing at the given time nav_stop stop playback nav_pause pause playback nav_resumeplay resume playback at normal speed nav_nexttrack continue with next track nav_previoustrack continue with previous track nav_repeat set the repeat mode for playback nav_repeatab set the repeat ab mode nav_shuf?e play tracks in random order nav_introscan play only intro part of each track nav_forwardscan start scanning forward C fast playback with burst sound nav_backwardscan start scanning backward C fast playback with burst sound nav_setplaysequence set play sequence mode nav_setprogramlist set program list nav_getstate returns navigator states nav_getplaylist returns navigator play list post-processing api apm_setspeakers select speaker con?guration apm_setinputmode select between dsd or pcm as apm input apm_setoutputmode select apm output mode (dsd or pcm) apm_set6chdownmix set the downmix of six-channel output stream apm_set2chdownmix set the downmix of two-channel output stream apm_setbassfilters select the bass management frequency and slope apm_setattenuation set attenuation of an output channel apm_setdelay set delay of a channel of output stream apm_setfiltermode set sigma delta modulator ?lter mode apm_setpcmupsampling set the pcm upsampling mode apm_setpio set the dac pio pins text and data api sdi_setavailablecharsets set a list of character sets, application can handle sdi_setlanguagepreference set a list of preferred languages sdi_getalbuminfo retrieve information about the album of active disc sdi_getalbumtext retrieve album text items
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 59 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 14.2 api required by sa-mp software to be provided by the dvd host: ? for the front-end: seek, getdataarea, transferrate (optional) ? for the operating system: tasks, interrupts, semaphores, mailboxes, timers. sdi_getnumberofindices retrieve number of indices for speci?ed track sdi_getdiscinfo retrieve information about the active disc sdi_getdisctext retrieve disc text items sdi_getareatext retrieve area text items sdi_gettrackinfo retrieve information about the speci?ed track sdi_gettracktext retrieve track text items system con?guration api sdm_setbetype select the front-end interface attached to sa-mp sdm_setdacpinnning con?gure the dac pins sdm_setaudioclock con?gure the audio clock for different input stream modes sdm_setmemorycon?g con?gure the sdram attached to the SAA7893hl sdm_gethandler return the pointer to sa-mp interrupt handler sdm_setdsdclockpolarity con?gure the dsd clock polarity sdm_setsystemclock inform sa-mp about the system clock sdm_setburstlength con?gure the burst length for fast play general api samp_init initialize sa-mp samp_term terminate sa-mp samp_activate activate sa-mp samp_reactivate reactivate sa-mp samp_deactivate deactivate sa-mp samp_sacddiscreq sacd disc recognition table 38: api provided by sa-mp continued name description
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 60 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 15. limiting values [1] stresses above the absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum ratings for extended periods may effect device reliability. 16. characteristics table 39: absolute maximum ratings in accordance with the absolute maximum rating system (iec 60134). note 1 . symbol parameter min max unit vcc_core digital core supply voltage - 0.5 + 2.1 v vcc_io io pins supply voltage - 0.5 + 3.8 v v dda analog supply voltage - 0.5 + 2.1 v v i dc input voltage - 0.5 + 5.5 v t amb ambient temperature 0 70 c t stg storage temperature - 25 + 125 c t j junction temperature - 150 + 150 c table 40: characteristics symbol parameter min typ max unit power supply: vcc_core (digital core supply voltage) vcc_core digital core supply voltage 1.65 1.8 1.95 v p power dissipation 90 110 150 mw power supply: v dda (analog supply voltage) v dda analog supply voltage 1.65 1.8 1.95 v p power dissipation during disc recognition only - 40 60 mw power supply: vcc_io (i/o pins supply voltage) vcc_io i/o pins supply voltage 3.0 3.3 3.6 v p power dissipation during disc recognition only - 70 100 mw digital inputs and outputs v ih high-level input voltage 2.0 - vcc_io + 0.5 v v il low-level input voltage - - 0.8 v v oh high-level output voltage vcc_io - 0.4 - - v v ol low-level output voltage - - 0.4 v c i input capacitance - - 10 pf c o output capacitance - - 10 pf i li input leakage current - - 10 m a i i(n) input current on any pin except supplies - - 10 ma
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 61 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 17. package outline fig 60. lqfp128 (sot425-1) package outline. unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.15 15.85 0.81 0.59 7 0 o o 0.12 0.2 0.1 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot425-1 136e28 ms-026 99-12-27 00-01-19 d (1) (1) (1) 20.1 19.9 h d 22.15 21.85 e z 0.81 0.59 d 0 5 10 mm scale b p e q e a 1 a l p detail x l (a ) 3 b c b p e h a 2 d h v m b d z d a z e e v m a x 102 103 y w m w m a max. 1.6 lqfp128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm sot425-1 65 64 38 39 1 128 pin 1 index
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 62 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 18. soldering 18.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 18.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferably be kept: ? below 220 c for all the bga packages and packages with a thickness 3 2.5mm and packages with a thickness <2.5 mm and a volume 3 350 mm 3 so called thick/large packages ? below 235 c for packages with a thickness <2.5 mm and a volume <350 mm 3 so called small/thin packages. 18.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end.
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 63 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 18.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 18.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [4] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [5] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [6] wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. table 41: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable [3] suitable plcc [4] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [4][5] suitable ssop, tssop, vso, vssop not recommended [6] suitable
philips semiconductors SAA7893hl super audio media player product data rev. 02 26 february 2003 64 of 66 9397 750 10925 ? koninklijke philips electronics n.v. 2003. all rights reserved. 19. revision history table 42: revision history rev date cpcn description 02 20030226 - product data (9397 750 10925) modi?cations: ? the value of the capacitor to pin adcre? in figure 44 is changed from 10 nf to 100 nf ? the system clock de?nitions are added in section 7.5.1 ? the audio clock de?nitions are added in section 7.5.2 ? a remark is added at the end of section 8.2 . ? a note is added to ta b l e 1 1 . 01 20021014 - product data (9397 750 10341)
9397 750 10925 philips semiconductors SAA7893hl super audio media player ? koninklijke philips electronics n.v. 2003. all rights reserved. product data rev. 02 26 february 2003 65 of 66 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 20. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 21. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 22. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 23. trademarks dolby available only to licensees of dolby laboratories licensing corporation, san francisco, ca94111, usa, from whom licensing and application information must be obtained. dolby is a registered trade-mark of dolby laboratories licensing corporation. level data sheet status [1] product status [2][3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2003. printed in the netherlands all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 26 february 2003 document order number: 9397 750 10925 contents philips semiconductors SAA7893hl super audio media player 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 1.1 hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 components . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 hw interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.3 sw interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.4 system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.5 system con?guration . . . . . . . . . . . . . . . . . . . . 4 2.6 sacd playback. . . . . . . . . . . . . . . . . . . . . . . . . 4 2.7 audio postprocessing . . . . . . . . . . . . . . . . . . . . 4 2.8 sacd data and text . . . . . . . . . . . . . . . . . . . . . 5 2.9 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 ordering information . . . . . . . . . . . . . . . . . . . . . 6 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 7 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.1 host interface . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.2 front-end interface . . . . . . . . . . . . . . . . . . . . . 11 7.3 audio interface . . . . . . . . . . . . . . . . . . . . . . . . 12 7.4 sdram interface . . . . . . . . . . . . . . . . . . . . . . 12 7.5 clock and reset input . . . . . . . . . . . . . . . . . . . 12 7.6 test inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1 general description. . . . . . . . . . . . . . . . . . . . . 14 8.2 sad16_01/02 mode . . . . . . . . . . . . . . . . . . . . 15 8.3 sad16_03 mode . . . . . . . . . . . . . . . . . . . . . . 19 8.4 mad16_01 mode . . . . . . . . . . . . . . . . . . . . . . 25 8.5 mad16_02 mode . . . . . . . . . . . . . . . . . . . . . . 30 8.6 sad08 mode . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.7 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 front-end interface . . . . . . . . . . . . . . . . . . . . . 37 9.1 i 2 s-bus interface . . . . . . . . . . . . . . . . . . . . . . . 38 9.2 ude data interface . . . . . . . . . . . . . . . . . . . . . 40 9.3 fec interface . . . . . . . . . . . . . . . . . . . . . . . . . 43 10 hf input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.2 hf input speci?cation . . . . . . . . . . . . . . . . . . . 45 10.3 hf-input application diagram . . . . . . . . . . . . . 46 11 audio interfaces. . . . . . . . . . . . . . . . . . . . . . . . 46 11.1 audio input interface . . . . . . . . . . . . . . . . . . . . 46 11.2 audio output interface . . . . . . . . . . . . . . . . . . . 47 11.3 audio output application diagrams . . . . . . . . . 51 12 sdram interface . . . . . . . . . . . . . . . . . . . . . . . 54 12.1 writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12.2 reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12.3 interface connection . . . . . . . . . . . . . . . . . . . . 56 13 power supply connections . . . . . . . . . . . . . . . 57 14 software api . . . . . . . . . . . . . . . . . . . . . . . . . . 58 14.1 api provided by sa-mp . . . . . . . . . . . . . . . . . 58 14.2 api required by sa-mp . . . . . . . . . . . . . . . . . 59 15 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 60 16 characteristics . . . . . . . . . . . . . . . . . . . . . . . . 60 17 package outline . . . . . . . . . . . . . . . . . . . . . . . . 61 18 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 18.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 18.2 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 62 18.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 62 18.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 63 18.5 package related soldering information . . . . . . 63 19 revision history . . . . . . . . . . . . . . . . . . . . . . . 64 20 data sheet status. . . . . . . . . . . . . . . . . . . . . . . 65 21 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 22 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 23 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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